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Timo Niemann
2026-06-04 10:21:56 +02:00
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FreeRTOS/portable/GCC/AVR32_UC3/exception.S
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/*
* FreeRTOS Kernel V11.3.0
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT AND BSD-3-Clause
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Exception and interrupt vectors.
*
* This file maps all events supported by an AVR32UC.
*
* - Compiler: GNU GCC for AVR32
* - Supported devices: All AVR32UC devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation (Now Microchip):
* https://www.microchip.com \n
* Support and FAQ: https://www.microchip.com/support/
*
******************************************************************************/
/*
* Copyright (c) 2007, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <avr32/io.h>
#include "intc.h"
//! @{
//! \verbatim
.section .exception, "ax", @progbits
// Start of Exception Vector Table.
// EVBA must be aligned with a power of two strictly greater than the EVBA-
// relative offset of the last vector.
.balign 0x200
// Export symbol.
.global _evba
.type _evba, @function
_evba:
.org 0x000
// Unrecoverable Exception.
_handle_Unrecoverable_Exception:
rjmp $
.org 0x004
// TLB Multiple Hit: UNUSED IN AVR32UC.
_handle_TLB_Multiple_Hit:
rjmp $
.org 0x008
// Bus Error Data Fetch.
_handle_Bus_Error_Data_Fetch:
rjmp $
.org 0x00C
// Bus Error Instruction Fetch.
_handle_Bus_Error_Instruction_Fetch:
rjmp $
.org 0x010
// NMI.
_handle_NMI:
rjmp $
.org 0x014
// Instruction Address.
_handle_Instruction_Address:
rjmp $
.org 0x018
// ITLB Protection.
_handle_ITLB_Protection:
rjmp $
.org 0x01C
// Breakpoint.
_handle_Breakpoint:
rjmp $
.org 0x020
// Illegal Opcode.
_handle_Illegal_Opcode:
rjmp $
.org 0x024
// Unimplemented Instruction.
_handle_Unimplemented_Instruction:
rjmp $
.org 0x028
// Privilege Violation.
_handle_Privilege_Violation:
rjmp $
.org 0x02C
// Floating-Point: UNUSED IN AVR32UC.
_handle_Floating_Point:
rjmp $
.org 0x030
// Coprocessor Absent: UNUSED IN AVR32UC.
_handle_Coprocessor_Absent:
rjmp $
.org 0x034
// Data Address (Read).
_handle_Data_Address_Read:
rjmp $
.org 0x038
// Data Address (Write).
_handle_Data_Address_Write:
rjmp $
.org 0x03C
// DTLB Protection (Read).
_handle_DTLB_Protection_Read:
rjmp $
.org 0x040
// DTLB Protection (Write).
_handle_DTLB_Protection_Write:
rjmp $
.org 0x044
// DTLB Modified: UNUSED IN AVR32UC.
_handle_DTLB_Modified:
rjmp $
.org 0x050
// ITLB Miss: UNUSED IN AVR32UC.
_handle_ITLB_Miss:
rjmp $
.org 0x060
// DTLB Miss (Read): UNUSED IN AVR32UC.
_handle_DTLB_Miss_Read:
rjmp $
.org 0x070
// DTLB Miss (Write): UNUSED IN AVR32UC.
_handle_DTLB_Miss_Write:
rjmp $
.org 0x100
// Supervisor Call.
_handle_Supervisor_Call:
lda.w pc, SCALLYield
// Interrupt support.
// The interrupt controller must provide the offset address relative to EVBA.
// Important note:
// All interrupts call a C function named _get_interrupt_handler.
// This function will read group and interrupt line number to then return in
// R12 a pointer to a user-provided interrupt handler.
.balign 4
_int0:
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry.
#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
mfsr r12, AVR32_SR
bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
cp.w r12, 0b110
brlo _int0_normal
lddsp r12, sp[0 * 4]
stdsp sp[6 * 4], r12
lddsp r12, sp[1 * 4]
stdsp sp[7 * 4], r12
lddsp r12, sp[3 * 4]
sub sp, -6 * 4
rete
_int0_normal:
#endif
mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
_int1:
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry.
#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
mfsr r12, AVR32_SR
bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
cp.w r12, 0b110
brlo _int1_normal
lddsp r12, sp[0 * 4]
stdsp sp[6 * 4], r12
lddsp r12, sp[1 * 4]
stdsp sp[7 * 4], r12
lddsp r12, sp[3 * 4]
sub sp, -6 * 4
rete
_int1_normal:
#endif
mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
_int2:
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry.
#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
mfsr r12, AVR32_SR
bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
cp.w r12, 0b110
brlo _int2_normal
lddsp r12, sp[0 * 4]
stdsp sp[6 * 4], r12
lddsp r12, sp[1 * 4]
stdsp sp[7 * 4], r12
lddsp r12, sp[3 * 4]
sub sp, -6 * 4
rete
_int2_normal:
#endif
mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
_int3:
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry.
#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
mfsr r12, AVR32_SR
bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
cp.w r12, 0b110
brlo _int3_normal
lddsp r12, sp[0 * 4]
stdsp sp[6 * 4], r12
lddsp r12, sp[1 * 4]
stdsp sp[7 * 4], r12
lddsp r12, sp[3 * 4]
sub sp, -6 * 4
rete
_int3_normal:
#endif
mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
// Constant data area.
.balign 4
// Values to store in the interrupt priority registers for the various interrupt priority levels.
// The interrupt priority registers contain the interrupt priority level and
// the EVBA-relative interrupt vector offset.
.global ipr_val
.type ipr_val, @object
ipr_val:
.word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
(INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
(INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
(INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
//! \endverbatim
//! @}
FreeRTOS/portable/GCC/AVR32_UC3/port.c
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/*
* FreeRTOS Kernel V11.3.0
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT AND BSD-3-Clause
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief FreeRTOS port source for AVR32 UC3.
*
* - Compiler: GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
*
* \author Atmel Corporation (Now Microchip):
* https://www.microchip.com \n
* Support and FAQ: https://www.microchip.com/support/
*
*****************************************************************************/
/*
* Copyright (c) 2007, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Standard includes. */
#include <sys/cpu.h>
#include <sys/usart.h>
#include <malloc.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* AVR32 UC3 includes. */
#include <avr32/io.h>
#include "gpio.h"
#if ( configTICK_USE_TC == 1 )
#include "tc.h"
#endif
/* Constants required to setup the task context. */
#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 )
/* Each task maintains its own critical nesting variable. */
#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
volatile uint32_t ulCriticalNesting = 9999UL;
#if ( configTICK_USE_TC == 0 )
static void prvScheduleNextTick( void );
#else
static void prvClearTcInt( void );
#endif
/* Setup the timer to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
/*
* Low-level initialization routine called during startup, before the main
* function.
* This version comes in replacement to the default one provided by Newlib.
* Newlib's _init_startup only calls init_exceptions, but Newlib's exception
* vectors are not compatible with the SCALL management in the current FreeRTOS
* port. More low-level initializations are besides added here.
*/
void _init_startup( void )
{
/* Import the Exception Vector Base Address. */
extern void _evba;
#if configHEAP_INIT
extern void __heap_start__;
extern void __heap_end__;
BaseType_t * pxMem;
#endif
/* Load the Exception Vector Base Address in the corresponding system register. */
Set_system_register( AVR32_EVBA, ( int ) &_evba );
/* Enable exceptions. */
ENABLE_ALL_EXCEPTIONS();
/* Initialize interrupt handling. */
INTC_init_interrupts();
#if configHEAP_INIT
/* Initialize the heap used by malloc. */
for( pxMem = &__heap_start__; pxMem < ( BaseType_t * ) &__heap_end__; )
{
*pxMem++ = 0xA5A5A5A5;
}
#endif
/* Give the used CPU clock frequency to Newlib, so it can work properly. */
set_cpu_hz( configCPU_CLOCK_HZ );
/* Code section present if and only if the debug trace is activated. */
#if configDBG
{
static const gpio_map_t DBG_USART_GPIO_MAP =
{
{ configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
{ configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
};
/* Initialize the USART used for the debug trace with the configured parameters. */
set_usart_base( ( void * ) configDBG_USART );
gpio_enable_module( DBG_USART_GPIO_MAP,
sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[ 0 ] ) );
usart_init( configDBG_USART_BAUDRATE );
}
#endif /* if configDBG */
}
/*-----------------------------------------------------------*/
/*
* malloc, realloc and free are meant to be called through respectively
* pvPortMalloc, pvPortRealloc and vPortFree.
* The latter functions call the former ones from within sections where tasks
* are suspended, so the latter functions are task-safe. __malloc_lock and
* __malloc_unlock use the same mechanism to also keep the former functions
* task-safe as they may be called directly from Newlib's functions.
* However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE
* CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do
* not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable
* interrupts during memory allocation management as this may be a very time-
* consuming process.
*/
/*
* Lock routine called by Newlib on malloc / realloc / free entry to guarantee a
* safe section as memory allocation management uses global data.
* See the aforementioned details.
*/
void __malloc_lock( struct _reent * ptr )
{
vTaskSuspendAll();
}
/*
* Unlock routine called by Newlib on malloc / realloc / free exit to guarantee
* a safe section as memory allocation management uses global data.
* See the aforementioned details.
*/
void __malloc_unlock( struct _reent * ptr )
{
xTaskResumeAll();
}
/*-----------------------------------------------------------*/
/* Added as there is no such function in FreeRTOS. */
void * pvPortRealloc( void * pv,
size_t xWantedSize )
{
void * pvReturn;
vTaskSuspendAll();
{
pvReturn = realloc( pv, xWantedSize );
}
xTaskResumeAll();
return pvReturn;
}
/*-----------------------------------------------------------*/
/* The cooperative scheduler requires a normal IRQ service routine to
* simply increment the system tick. */
/* The preemptive scheduler is defined as "naked" as the full context is saved
* on entry as part of the context switch. */
__attribute__( ( __naked__ ) ) static void vTick( void )
{
/* Save the context of the interrupted task. */
portSAVE_CONTEXT_OS_INT();
#if ( configTICK_USE_TC == 1 )
/* Clear the interrupt flag. */
prvClearTcInt();
#else
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
* clock cycles from now. */
prvScheduleNextTick();
#endif
/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
* calls in a critical section . */
portENTER_CRITICAL();
xTaskIncrementTick();
portEXIT_CRITICAL();
/* Restore the context of the "elected task". */
portRESTORE_CONTEXT_OS_INT();
}
/*-----------------------------------------------------------*/
__attribute__( ( __naked__ ) ) void SCALLYield( void )
{
/* Save the context of the interrupted task. */
portSAVE_CONTEXT_SCALL();
vTaskSwitchContext();
portRESTORE_CONTEXT_SCALL();
}
/*-----------------------------------------------------------*/
/* The code generated by the GCC compiler uses the stack in different ways at
* different optimisation levels. The interrupt flags can therefore not always
* be saved to the stack. Instead the critical section nesting level is stored
* in a variable, which is then saved as part of the stack context. */
__attribute__( ( __noinline__ ) ) void vPortEnterCritical( void )
{
/* Disable interrupts */
portDISABLE_INTERRUPTS();
/* Now that interrupts are disabled, ulCriticalNesting can be accessed
* directly. Increment ulCriticalNesting to keep a count of how many times
* portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
__attribute__( ( __noinline__ ) ) void vPortExitCritical( void )
{
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
ulCriticalNesting--;
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable all interrupt/exception. */
portENABLE_INTERRUPTS();
}
}
}
/*-----------------------------------------------------------*/
/*
* Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
* expected by the portRESTORE_CONTEXT() macro. */
/* When the task starts, it will expect to find the function parameter in R12. */
pxTopOfStack--;
*pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */
*pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */
*pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */
*pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */
*pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */
*pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */
*pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
*pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */
*pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */
*pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */
*pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */
*pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */
*pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */
*pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */
*pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */
*pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */
*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
portRESTORE_CONTEXT();
/* Should not get here! */
return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the AVR32 port will require this function as there
* is nothing to return to. */
}
/*-----------------------------------------------------------*/
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
* clock cycles from now. */
#if ( configTICK_USE_TC == 0 )
static void prvScheduleFirstTick( void )
{
uint32_t lCycles;
lCycles = Get_system_register( AVR32_COUNT );
lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
/* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
/* generation feature does not get disabled. */
if( 0 == lCycles )
{
lCycles++;
}
Set_system_register( AVR32_COMPARE, lCycles );
}
__attribute__( ( __noinline__ ) ) static void prvScheduleNextTick( void )
{
uint32_t lCycles, lCount;
lCycles = Get_system_register( AVR32_COMPARE );
lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
/* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
/* generation feature does not get disabled. */
if( 0 == lCycles )
{
lCycles++;
}
lCount = Get_system_register( AVR32_COUNT );
if( lCycles < lCount )
{ /* We missed a tick, recover for the next. */
lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
}
Set_system_register( AVR32_COMPARE, lCycles );
}
#else /* if ( configTICK_USE_TC == 0 ) */
__attribute__( ( __noinline__ ) ) static void prvClearTcInt( void )
{
AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr;
}
#endif /* if ( configTICK_USE_TC == 0 ) */
/*-----------------------------------------------------------*/
/* Setup the timer to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void )
{
#if ( configTICK_USE_TC == 1 )
volatile avr32_tc_t * tc = &AVR32_TC;
/* Options for waveform generation. */
tc_waveform_opt_t waveform_opt =
{
.channel = configTICK_TC_CHANNEL, /* Channel selection. */
.bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
.beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
.bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
.bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
.aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
.aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
.acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
.acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER, /* Waveform selection: Up mode without automatic trigger on RC compare. */
.enetrg = FALSE, /* External event trigger enable. */
.eevt = 0, /* External event selection. */
.eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
.cpcdis = FALSE, /* Counter disable when RC compare. */
.cpcstop = FALSE, /* Counter clock stopped with RC compare. */
.burst = FALSE, /* Burst signal selection. */
.clki = FALSE, /* Clock inversion. */
.tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
};
tc_interrupt_t tc_interrupt =
{
.etrgs = 0,
.ldrbs = 0,
.ldras = 0,
.cpcs = 1,
.cpbs = 0,
.cpas = 0,
.lovrs = 0,
.covfs = 0,
};
#endif /* if ( configTICK_USE_TC == 1 ) */
/* Disable all interrupt/exception. */
portDISABLE_INTERRUPTS();
/* Register the compare interrupt handler to the interrupt controller and
* enable the compare interrupt. */
#if ( configTICK_USE_TC == 1 )
{
INTC_register_interrupt( &vTick, configTICK_TC_IRQ, INT0 );
/* Initialize the timer/counter. */
tc_init_waveform( tc, &waveform_opt );
/* Set the compare triggers.
* Remember TC counter is 16-bits, so counting second is not possible!
* That's why we configure it to count ms. */
tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4 ) / configTICK_RATE_HZ );
tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
/* Start the timer/counter. */
tc_start( tc, configTICK_TC_CHANNEL );
}
#else /* if ( configTICK_USE_TC == 1 ) */
{
INTC_register_interrupt( &vTick, AVR32_CORE_COMPARE_IRQ, INT0 );
prvScheduleFirstTick();
}
#endif /* if ( configTICK_USE_TC == 1 ) */
}
FreeRTOS/portable/GCC/AVR32_UC3/portmacro.h
+704
View File
@@ -0,0 +1,704 @@
/*
* FreeRTOS Kernel V11.3.0
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT AND BSD-3-Clause
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief FreeRTOS port source for AVR32 UC3.
*
* - Compiler: GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
*
* \author Atmel Corporation (Now Microchip):
* https://www.microchip.com \n
* Support and FAQ: https://www.microchip.com/support/
*
*****************************************************************************/
/*
* Copyright (c) 2007, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
#include <avr32/io.h>
#include "intc.h"
#include "compiler.h"
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE uint32_t
#define portBASE_TYPE long
typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t;
typedef unsigned long UBaseType_t;
#define TASK_DELAY_MS( x ) ( ( x ) / portTICK_PERIOD_MS )
#define TASK_DELAY_S( x ) ( ( x ) * 1000 / portTICK_PERIOD_MS )
#define TASK_DELAY_MIN( x ) ( ( x ) * 60 * 1000 / portTICK_PERIOD_MS )
#define configTICK_TC_IRQ ATPASTE2( AVR32_TC_IRQ, configTICK_TC_CHANNEL )
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL )
#else
#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 4
#define portNOP() { __asm__ __volatile__ ( "nop" ); }
/*-----------------------------------------------------------*/
/*-----------------------------------------------------------*/
/* INTC-specific. */
#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
#define DISABLE_INT_LEVEL( int_lev ) Disable_interrupt_level( int_lev )
#define ENABLE_INT_LEVEL( int_lev ) Enable_interrupt_level( int_lev )
/*
* Debug trace.
* Activated if and only if configDBG is nonzero.
* Prints a formatted string to stdout.
* The current source file name and line number are output with a colon before
* the formatted string.
* A carriage return and a linefeed are appended to the output.
* stdout is redirected to the USART configured by configDBG_USART.
* The parameters are the same as for the standard printf function.
* There is no return value.
* SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
* which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
*/
#if configDBG
#define portDBG_TRACE( ... ) \
{ \
fputs( __FILE__ ":" ASTRINGZ( __LINE__ ) ": ", stdout ); \
printf( __VA_ARGS__ ); \
fputs( "\r\n", stdout ); \
}
#else
#define portDBG_TRACE( ... )
#endif
/* Critical section management. */
#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
#define portENTER_CRITICAL() vPortEnterCritical();
#define portEXIT_CRITICAL() vPortExitCritical();
/* Added as there is no such function in FreeRTOS. */
extern void * pvPortRealloc( void * pv,
size_t xSize );
/*-----------------------------------------------------------*/
/*=============================================================================================*/
/*
* Restore Context for cases other than INTi.
*/
#define portRESTORE_CONTEXT() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
__asm__ __volatile__ ( \
/* Set SP to point to new stack */ \
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
"ld.w r0, r8[0] \n\t" \
"ld.w sp, r0[0] \n\t" \
\
/* Restore ulCriticalNesting variable */ \
"ld.w r0, sp++ \n\t" \
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
"st.w r8[0], r0 \n\t" \
\
/* Restore R0..R7 */ \
"ldm sp++, r0-r7 \n\t" \
/* R0-R7 should not be used below this line */ \
/* Skip PC and SR (will do it at the end) */ \
"sub sp, -2*4 \n\t" \
/* Restore R8..R12 and LR */ \
"ldm sp++, r8-r12, lr \n\t" \
/* Restore SR */ \
"ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
"mtsr %[SR], r0 \n\t" \
/* Restore r0 */ \
"ld.w r0, sp[-9*4] \n\t" \
/* Restore PC */ \
"ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
: \
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
[ SR ] "i" ( AVR32_SR ) \
); \
}
/*
* portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
* portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
*
* Had to make different versions because registers saved on the system stack
* are not the same between INT0..3 exceptions and the scall exception.
*/
/* Task context stack layout: */
/* R8 (*) */
/* R9 (*) */
/* R10 (*) */
/* R11 (*) */
/* R12 (*) */
/* R14/LR (*) */
/* R15/PC (*) */
/* SR (*) */
/* R0 */
/* R1 */
/* R2 */
/* R3 */
/* R4 */
/* R5 */
/* R6 */
/* R7 */
/* ulCriticalNesting */
/* (*) automatically done for INT0..INT3, but not for SCALL */
/*
* The ISR used for the scheduler tick depends on whether the cooperative or
* the preemptive scheduler is being used.
*/
#if configUSE_PREEMPTION == 0
/*
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
*/
#define portSAVE_CONTEXT_OS_INT() \
{ \
/* Save R0..R7 */ \
__asm__ __volatile__ ( "stm --sp, r0-r7" ); \
\
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
/* there is also no context save. */ \
}
/*
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
*/
#define portRESTORE_CONTEXT_OS_INT() \
{ \
__asm__ __volatile__ ( \
/* Restore R0..R7 */ \
"ldm sp++, r0-r7\n\t" \
\
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
/* there is also no context restore. */ \
"rete" \
); \
}
#else /* if configUSE_PREEMPTION == 0 */
/*
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
*/
#define portSAVE_CONTEXT_OS_INT() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
/* When we come here */ \
/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
\
__asm__ __volatile__ ( \
/* Save R0..R7 */ \
"stm --sp, r0-r7 \n\t" \
\
/* Save ulCriticalNesting variable - R0 is overwritten */ \
"mov r8, LO(%[ulCriticalNesting])\n\t" \
"orh r8, HI(%[ulCriticalNesting])\n\t" \
"ld.w r0, r8[0] \n\t" \
"st.w --sp, r0 \n\t" \
\
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
/* level and allow other lower interrupt level to occur). */ \
/* In this case we don't want to do a task switch because we don't know what the stack */ \
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
/* will just be restoring the interrupt handler, no way!!! */ \
/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
"ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
"bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
"cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
"brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \
\
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
/* NOTE: we don't enter a critical section here because all interrupt handlers */ \
/* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
/* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
/* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
"mov r8, LO(%[pxCurrentTCB])\n\t" \
"orh r8, HI(%[pxCurrentTCB])\n\t" \
"ld.w r0, r8[0]\n\t" \
"st.w r0[0], sp\n" \
\
"LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
: \
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
[ LINE ] "i" ( __LINE__ ) \
); \
}
/*
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
*/
#define portRESTORE_CONTEXT_OS_INT() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
/* level and allow other lower interrupt level to occur). */ \
/* In this case we don't want to do a task switch because we don't know what the stack */ \
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
/* will just be restoring the interrupt handler, no way!!! */ \
__asm__ __volatile__ ( \
"ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
"bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
"cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
"brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
: \
:[ LINE ] "i" ( __LINE__ ) \
); \
\
/* Else */ \
/* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
portENTER_CRITICAL(); \
vTaskSwitchContext(); \
portEXIT_CRITICAL(); \
\
/* Restore all registers */ \
\
__asm__ __volatile__ ( \
/* Set SP to point to new stack */ \
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
"ld.w r0, r8[0] \n\t" \
"ld.w sp, r0[0] \n" \
\
"LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \
\
/* Restore ulCriticalNesting variable */ \
"ld.w r0, sp++ \n\t" \
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
"st.w r8[0], r0 \n\t" \
\
/* Restore R0..R7 */ \
"ldm sp++, r0-r7 \n\t" \
\
/* Now, the stack should be R8..R12, LR, PC and SR */ \
"rete" \
: \
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
[ LINE ] "i" ( __LINE__ ) \
); \
}
#endif /* if configUSE_PREEMPTION == 0 */
/*
* portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
*
* NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
*
*/
#define portSAVE_CONTEXT_SCALL() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
/* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
/* If SR[M2:M0] == 001 */ \
/* PC and SR are on the stack. */ \
/* Else (other modes) */ \
/* Nothing on the stack. */ \
\
/* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
/* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
/* in an interrupt|exception handler. */ \
\
__asm__ __volatile__ ( \
/* in order to save R0-R7 */ \
"sub sp, 6*4 \n\t" \
/* Save R0..R7 */ \
"stm --sp, r0-r7 \n\t" \
\
/* in order to save R8-R12 and LR */ \
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
"sub r7, sp,-16*4 \n\t" \
/* Copy PC and SR in other places in the stack. */ \
"ld.w r0, r7[-2*4] \n\t" /* Read SR */ \
"st.w r7[-8*4], r0 \n\t" /* Copy SR */ \
"ld.w r0, r7[-1*4] \n\t" /* Read PC */ \
"st.w r7[-7*4], r0 \n\t" /* Copy PC */ \
\
/* Save R8..R12 and LR on the stack. */ \
"stm --r7, r8-r12, lr \n\t" \
\
/* Arriving here we have the following stack organizations: */ \
/* R8..R12, LR, PC, SR, R0..R7. */ \
\
/* Now we can finalize the save. */ \
\
/* Save ulCriticalNesting variable - R0 is overwritten */ \
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
"ld.w r0, r8[0] \n\t" \
"st.w --sp, r0" \
: \
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \
); \
\
/* Disable the its which may cause a context switch (i.e. cause a change of */ \
/* pxCurrentTCB). */ \
/* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
/* critical section because it is a global structure. */ \
portENTER_CRITICAL(); \
\
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
__asm__ __volatile__ ( \
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
"ld.w r0, r8[0] \n\t" \
"st.w r0[0], sp" \
: \
:[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
); \
}
/*
* portRESTORE_CONTEXT() for SupervisorCALL exception.
*/
#define portRESTORE_CONTEXT_SCALL() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
/* Restore all registers */ \
\
/* Set SP to point to new stack */ \
__asm__ __volatile__ ( \
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
"ld.w r0, r8[0] \n\t" \
"ld.w sp, r0[0]" \
: \
:[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
); \
\
/* Leave pxCurrentTCB variable access critical section */ \
portEXIT_CRITICAL(); \
\
__asm__ __volatile__ ( \
/* Restore ulCriticalNesting variable */ \
"ld.w r0, sp++ \n\t" \
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
"st.w r8[0], r0 \n\t" \
\
/* skip PC and SR */ \
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
"sub r7, sp, -10*4 \n\t" \
/* Restore r8-r12 and LR */ \
"ldm r7++, r8-r12, lr \n\t" \
\
/* RETS will take care of the extra PC and SR restore. */ \
/* So, we have to prepare the stack for this. */ \
"ld.w r0, r7[-8*4] \n\t" /* Read SR */ \
"st.w r7[-2*4], r0 \n\t" /* Copy SR */ \
"ld.w r0, r7[-7*4] \n\t" /* Read PC */ \
"st.w r7[-1*4], r0 \n\t" /* Copy PC */ \
\
/* Restore R0..R7 */ \
"ldm sp++, r0-r7 \n\t" \
\
"sub sp, -6*4 \n\t" \
\
"rets" \
: \
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \
); \
}
/*
* The ISR used depends on whether the cooperative or
* the preemptive scheduler is being used.
*/
#if configUSE_PREEMPTION == 0
/*
* ISR entry and exit macros. These are only required if a task switch
* is required from the ISR.
*/
#define portENTER_SWITCHING_ISR() \
{ \
/* Save R0..R7 */ \
__asm__ __volatile__ ( "stm --sp, r0-r7" ); \
\
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
/* there is also no context save. */ \
}
/*
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
*/
#define portEXIT_SWITCHING_ISR() \
{ \
__asm__ __volatile__ ( \
/* Restore R0..R7 */ \
"ldm sp++, r0-r7 \n\t" \
\
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
/* there is also no context restore. */ \
"rete" \
); \
}
#else /* if configUSE_PREEMPTION == 0 */
/*
* ISR entry and exit macros. These are only required if a task switch
* is required from the ISR.
*/
#define portENTER_SWITCHING_ISR() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
/* When we come here */ \
/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
\
__asm__ __volatile__ ( \
/* Save R0..R7 */ \
"stm --sp, r0-r7 \n\t" \
\
/* Save ulCriticalNesting variable - R0 is overwritten */ \
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
"ld.w r0, r8[0] \n\t" \
"st.w --sp, r0 \n\t" \
\
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
/* level and allow other lower interrupt level to occur). */ \
/* In this case we don't want to do a task switch because we don't know what the stack */ \
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
/* will just be restoring the interrupt handler, no way!!! */ \
/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
"brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \
\
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
"ld.w r0, r8[0] \n\t" \
"st.w r0[0], sp \n" \
\
"LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
: \
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
[ LINE ] "i" ( __LINE__ ) \
); \
}
/*
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
*/
#define portEXIT_SWITCHING_ISR() \
{ \
extern volatile uint32_t ulCriticalNesting; \
extern volatile void * volatile pxCurrentTCB; \
\
__asm__ __volatile__ ( \
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
/* level and allow other lower interrupt level to occur). */ \
/* In this case it's of no use to switch context and restore a new SP because we purposely */ \
/* did not previously save SP in its TCB. */ \
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
"brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t" \
\
/* If a switch is required then we just need to call */ \
/* vTaskSwitchContext() as the context has already been */ \
/* saved. */ \
"cp.w r12, 1 \n\t" /* Check if Switch context is required. */ \
"brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
: \
:[ LINE ] "i" ( __LINE__ ) \
); \
\
/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
portENTER_CRITICAL(); \
vTaskSwitchContext(); \
portEXIT_CRITICAL(); \
\
__asm__ __volatile__ ( \
"LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t" \
/* Restore the context of which ever task is now the highest */ \
/* priority that is ready to run. */ \
\
/* Restore all registers */ \
\
/* Set SP to point to new stack */ \
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
"ld.w r0, r8[0] \n\t" \
"ld.w sp, r0[0] \n" \
\
"LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \
\
/* Restore ulCriticalNesting variable */ \
"ld.w r0, sp++ \n\t" \
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
"st.w r8[0], r0 \n\t" \
\
/* Restore R0..R7 */ \
"ldm sp++, r0-r7 \n\t" \
\
/* Now, the stack should be R8..R12, LR, PC and SR */ \
"rete" \
: \
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
[ LINE ] "i" ( __LINE__ ) \
); \
}
#endif /* if configUSE_PREEMPTION == 0 */
#define portYIELD() { __asm__ __volatile__ ( "scall" ); }
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
#endif /* PORTMACRO_H */